Overview

Description

In this position you will be part of a world-class Silicon design organization working with a team of highly talented engineers working on cutting-edge IP/SoC architectures, advanced Silicon design and process technologies, with tremendously exciting opportunities for industry-leading engineering innovations.

  • Build and develop validation test plans and test scenarios to prove the correctness of the design
  • Development of validation components for a simulation based environment, bus functional models, trackers, checkers, scoreboards, and testbenches
  • Building and delivery of an RTL model of the design – Performing and debugging simulations
  • Development of functional coverage and achieving coverage goals – Identifying and driving to closure of bugs
  • Developing methodologies and capabilities, and driving process improvements
  • Working closely with design engineers, micro-architects, and other team members to ensure high quality of test plans, functional coverage, and tests
  • Ability to deliver high-quality output against deadlines and able to work effectively in a cross-site team environment

Qualifications:

Bachelors or Masters degree in Electrical, Electronics or Computer Engineering with 2-8 years of relevant industry experience.

  • Good knowledge of digital logic design, IP/SoC architecture and microarchitecture.
  • Experience in OVM/UVM environment, developing testplans/testbenches, C-based transactors, and writing/debugging assembly based tests.
  • Experience with advanced verification techniques such as formal and assertions a plus.
  • Experience using an interpretive language such as Perl, Python or Ruby.
  • Experience in C or C++ programming a plus.
  • Experience in Post-Si bring-up is a big plus.
  • Strong analytical and debugging skills, and creative in problem solving.
  • Candidates with any of the below skills will fit for this requirement:
  • Performance verification or GPU verification
  • SOC verification
  • Emulation Engineers with experience in verification of design using emulation platform or FPGA prototyping.